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Q1. Define hierarchical modeling. Must each model level match the schematic exactly or can short cuts be taken to minimize modeling time without adversely affecting the overall multi-level model? A1. A hierarchical model is defined as two or more models linked together, with one model providing the architecture for the other. For example, A two level hierarhical LRU model would contain a top level model of the LRU and its SRAs and a lower level model of each SRA and its internal functional or component blocks. A three level LRU model would have the same two levels plus a third level for each block in each SRA. A two level SRA model would have a top level model reflecting the SRA and its components with lower level models for each component. Hierarchical modeling provides more information on signal flow than a single level model. A single or flat level LRU model would only indicate the I/O of each SRA, not the relationships between SRA outputs and inputs. The flat model defaults to all outputs depend on all inputs. A two or more level model would provide information on what inputs each output depends on. This provides far more information during analysis and knowledge base generation. Typically, for testing at one level, a two level model is sufficient. Extra levels provide some additional information on signal flow, but more often than not, not enough extra information to justify the added modeling time. If both LRU testing to the SRA level, and SRA testing to the component level were needed, a three level model would be required. The lowest model in a hierarchical model provides information that allows determination of signal flow at the higher level model. Thus, this model does not have to exactly reflect a schematic or functional block diagram. For example, for a two level LRU model, each SRA can be represented by component blocks or groups of functional blocks. The only criteria is that each output is tied to its associated inputs. The use of actual component names or functional blocks is not neccessary. The exception to this is if both LRU and SRA testing was to be done using the same model. In this case, the SRA model would have to contain actual components. Q2. Are component names important at the lowest level of a hierarchical model? A2. As mentioned above, the lowest level model is used to allow determination of signal flow at the next higher level. Component names are not important. If the lowest model is to be analyzed by itself, then component names are required to provide accurate analysis. Q3. List valid and invalid sources of EDIF/VHDL design data. A3. VALID: Designers CAD/CAE, OrCAD Manual Schematic Entry, and Manual creation. INVALID: PC Board Layout CAD/CAE, and Schematic Capture CAD/CAE. The EDIF must follow EDIF 2.0 or 3.0 format. The EDIF output of each CAD/CAE system must be analyzed independently to verify that the correct EDIF format is being used. Giordano Automation has found that some CAD/CAE systems state that they output standard EDIF, but in fact output a variation of EDIF. Giordano Automation designs translators to modify non-standard EDIF into standard EDIF. Q4. How should power and ground be modeled? A4. Power should be modeled as an input. Ground does not need to be modeled. If ground must be modeled, it should be designated an input. In general, when determining the direction of signals, if a failure of the signal will cause the design to fail, the signal is an input. If the design failing will cause the signal to fail, the signal is an output. If the signal is a bus, meaning it can both cause and be caused by a failure, it should be modeled as bidirectional. Note that when using the EDIF output of a CAD/CAE system, passive and bidirectional signals have the same EDIF definition: INOUT. Be careful when labeling signals as passive. Q5. How are package type components modeled if some of the parts are spares? A5. Package type components should be modeled exactly as shown. To eliminate the package parts that are spares, the Diagnostic Profiler provides a means to turn off specific pins. This is done by setting the frequency for that pin to 0. This is done using the Fault window of the Diagnostic Profiler.
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