EDIF Import Wizard

A design description formatted in EDIF can be automatically imported into the Diagnostic Profiler using the "EDIF Import Wizard." The EDIF Import Wizard takes you through a step-by-step process to import EDIF netlist files. The following paragraphs describe this process. The process includes a number of sequential steps, as follows:

Step 1 - Choose to Create New or Update Existing Project

Step 2 - Identify Project Name and Directory Location

Step 3 - Identify and Locate the EDIF Netlist to be Imported

Step 4 - Convert Reference Designators to Component Names (Only if Required)

Step 5 - Identify Power and Ground Signals

Step 6 - Identify Connectors

Step 7 - Identify the Internal Connectivity of Parts in the Circuit Design

Step 8 - Process Import Data

Throughout this process, press Next to proceed from one step to the next, and press Back to reverse back to previous steps. You can proceed back though as many steps as you wish, as often as you wish. You can exit the EDIF Import Wizard at any time after identifying the Project name and directory location, and data will not be lost when you return.

To Import an EDIF Netlist

2. Press Use Tool

or

Double Click on EDIF Import Wizard in the tool list.

The EDIF Import Wizard will appear. The EDIF Import Wizard will step you through the process of importing an EDIF netlist. EDIF File dialogue box will let you 1) Create a new project by importing a new EDIF file, and 2) Update an existing project by importing a revised EDIF file.

Step 1 - Choose to Create New or Update Existing Project

The first step in the EDIF Import process is to identify if the data to be imported is to be treated as a new project or an update to an existing project.

If the design data import represents a new project, press Next. If the import represents an update to an existing project, press "Update an Existing Project," and then Press "Next."

Step 2 - Identify Project Name and Directory Location

The second step in the import process involves identifying a name and directory location for the project to be created from the import. (screen graphic)

1. Enter a project name in the Name text box under "Import Design" You should use a name descriptive of the project. Often the same name as the EDIF netlist is used. The name is limited to 64 characters, and can include spaces.

2. Identify the directory location for the project to be created. You can use the browser window to traverse through your directory structure, or simply enter the full path in the text box labeled "Location." By default, the project directory will be placed in a subdirectory created under the \profiler\projects directory.

Once you have entered the information, press "Next" to proceed to the next step in the EDIF Import process.

Step 3 - Identify and Locate the EDIF Netlist to be Imported

Use the standard Windows Browse function to locate the location and name of the EDIF netlist file. (Screen graphic)

Press "Next" to proceed to the next step of the EDIF Import process.

Step 4 - Convert Reference Designators to Component Names

Instance Name Reference Options allows you to set the translator in a mode where it will convert EDIF file reference designations from an internally assigned CAD format to the proper component name references. This option is necessary when translating EDIF files generated from Mentor or ViewLogic CAD systems. In these systems, internally assigned reference designations precede the component names. The result is very difficult to read model data, which is hard to relate to printed schematics. Setting this option to "Yes" will cause the translator to strip out or convert the reference designations. If you don't know whether you need to use this option, press the Next button. If the component name listing on the following screen does not appear to have appropriate component names, press Back from that screen and select the Yes option, then press Next. (If you are familiar with EDIF, a quick scan of your EDIF file may indicate that this option is necessary.)

Press "Next" to proceed to the next step of the EDIF Import process.

Step 5 - Identify Power and Ground Signals

Step 5 involves identifying the signals that are Power and Ground. The translation tool will then treat power and ground signals appropriately and not include those signals within the signal flow of the circuitry. The screen includes a box on the left which lists all of the component locations and the signal associated with those locations. The Power and Ground locations should be identified to the translator by moving them to the list box on the right.

Locate and highlight power and ground locations by pressing the leftmost box corresponding to the signal. Press the "Pwr/Gnd->" box to move the signal from the left list box to the right list box. To highlight multiple items in the list box, press Ctrl while pointing and clicking on the additional items. The Search button allows you to search through the list for keywords, such as Vcc, Gnd, etc. The graphic shows an example of multiple power and ground signals selected.  The graphic shows an example of the items highlighted in the left list box moving to the right list box after pressing the "Pwr/Gnd->" button.

Use of Search to Locate Power and Ground Signals

You can use the Search function to locate and highlight either Nodes, Location Names or Part Types. Enter a string of characters into the text box, select the search type, and press Search to implement the search. All of the items that meet the search criteria established will be highlighted upon completion of the search. Use the scroll bar to review the resulting list. To take items away from the list, press Ctrl while pointing and clicking on the item you wish to remove. Press the "Pwr/Gnd->" button to move the selected items to the Power/Ground list box.

Press "Next" to proceed to the next step of the EDIF Import process.

Step 6 - Identify Connectors

A connector is often entered into a schematic as a distinct part. That part has numerous inputs and each input has a corresponding output, with a one-to-one relationship between the inputs and the outputs. However, the schematic interconnectivity often does not reflect the one-to-one correspondence of the input/output pins. The result in the model is that everything looks like it's tied to everything else - the circuit becomes one big feedback loop from an interconnectivity point of view. To fix this problem, the EDIF Import Wizard allows you to identify connector names. The EDIF translator will then treat the designated name as a connector, and will assume a direct input/output relationship among the pins.

The screen includes a box on the left which lists all of the part names and corresponding part type. The connector parts should be identified to the translator by moving them to the list box on the right.

Locate and highlight connector parts by pressing the leftmost box corresponding to the connector name. Press the "Connector->" box to move the part from the left list box to the right list box. To highlight multiple items in the list box, press Ctrl while pointing and clicking on the additional items. The Search button allows you to search through the list for keywords, such as P or J.

Press "Next" to proceed to the next step of the EDIF Import process.

Step 7 - Identify the Internal Connectivity of Parts in the Circuit Design

Sometimes, detailed interconnectivity information is not incorporated into a design or into an EDIF netlist describing the design. In these cases, the resulting signal flow and interconnectivity of the model results in more extensive interconnectivity than actually exists. This can be a nuisance when using the Profiler to define the coverage of tests. Rather than the Profiler providing you with an accurate list of reachable faults (directly reachable from fault location), the reachable list contains significantly more components than are reasonable. Consider a resistor pack containing ten resistors. From a schematic and signal flow point of view, these resistors may be implemented in totally distinct areas of circuitry. Yet, if the detailed interconnectivity (internal connections) of the resistor pack is not defined in the EDIF file, then the resulting Profiler model is not accurate. The EDIF Import Wizard contains a step that allows you to define the actual interconnectivity associated with such circuits.

Step 7 of the EDIF Import Wizard is optional and can be skipped by pressing the Next button.

If your design contains circuits such as described above, Step 7 enables you to define the actual interconnectivity of the circuits.

The main screen of Step 7 contains a drop-down list box of all parts in the design. To view the list of parts, press the arrow at the right of the list box.

Select the part that you want to add connectivity information to from the list in the list box.

The box at the left side of the screen lists the name and signal type (pin direction) of each pin of the part. You can change the pin direction by pressing on the box containing the signal type. A drop-down list will appear showing the list of signal types. Select the desired signal type by pressing to highlight, and click. The signal type of the pin will be modified according to your selection.

The box on the right side also contains the list of pins associated with the part. To define the actual interconnectivy of the pins, you break the pins out to distinct groups, and define the pins associated with each group. For example, assume a resistor pack containing two resistors. Pins 1 and 2 are the first resistor in the pack and pins 6 and 7 are the second resistor in the pack. To break these apart into they will be defined as belonging to separate groups. First, add a new group. Press the New Group pushbutton. A text entry box will be displayed. Enter the new group name (e.g., RESPACK-1). Next, add the pins to be assigned to that group, pins 1 and 2, by pressing the box at the left of the pin name. A check mark will appear in the box.

Next, define another new group (e.g., RESPACK-2), and again, assign the pins to be associated with that group. Next go back to the original group, (e.g., RESPACK), and unassign the pins from that group by clicking on the box at the left of the pin name to remove the checkmark.

You can see that two groups, RESPACK-1 and RESPACK-2 have been added to the list of groups associated with RESPACK by clicking on the drop-down box at the right of the screen.
 
From this screen, you can also remove groups and rename groups. However, this should be done with great care, since you are actually changing the overall design attributes. The goal here is to simply add a greater level of definition to the interconnectivity in the design than was provided in the original EDIF netlist.

Press "Next" to proceed to the next step of the EDIF Import process.

Step 8 - Process Import Data

The final step of the EDIF Import Process is to process the import data and criteria identified in the previous steps.

Press the button labeled "Import."

The progress of the EDIF translation is shown in the three bars in the screen display.

The newly created project will be loaded into the Diagnostic Profiler, with a single default candidate which has a single test, called Edge.
 

NOTE: The EDIF Translation process generates a series of messages, warnings, cautions and errors. This information is available as an Import Design Report. If your translation process ends up in an error, the report may provide more insight as to the cause of the error. It is recommended that you view the contents of this report. Errors should be fixed. Warnings and Cautions should be reviewed. These messages are also placed in an ASCII file called import.log in the project directory (\profiler\projects\<projectname>\import.log).
 

To update an existing project by importing a revised EDIF file

NOTE: After processing is complete, you can use the Design Changes Wizard to analyze the impact of the design changes on your project, including the coverage of tests previously defined.

Sample EDIF Netlist

The RF_CIRC2.NET EDIF file is installed in the \profiler\samples directory. Therefore, using the basic procedures identified here, you can translate the file as a sample.

A netlist for rf_circ which reflects a series of design changes is also provided. It is called rf_chngd.net, and can be used to sample the information provided via the Design Changes Wizard.

The .PWR File

The EDIF translator looks for a file which matches the netlist file name, but with the extension PWR. It reads this file and fixes all appropriate signals. If this file is not found, then the translator will use default convention names for Power and Ground. No defaults are incorporated for Connector designations. A warning will be displayed in the EDIF translation message window that the file was not found and defaults are being used.

The .PWR file is created in the project directory. Only one entry per line is allowed. The file is case sensitive.

Package Library File

The following information is provided for reference only.

The Package Library File is an ASCII text file having the same base name as the EDIF netlist file and with the extension PKG. For example, if the EDIF netlist file is 082.NET, the Package Library File is 082.PKG.

The Package Library File contains information about EDIF 'CELL' Library references for which no 'CONTENTS' information is provided (and thus no internal connectivity is available). To be used in a translation, the description in a Package Library File must:

1) Have the same name as the name in the EDIF netlist file (and the CAD package part type)

2) Have exactly the same number of pins as in the EDIF netlist file (and the CAD package part type)

3) Contain pins with exactly the same names (or numbers) as the pins specified in the EDIF netlist file (and the CAD package part type).

The Package Library File contains a sequence of specification statements. Each statement begins on a new line and ends with a semicolon. Each statement begins with a keyword that identifies which type of statement it is. The statement types are:

TYPE A statement which names a new package specification to be specified. This statement may also end the specification of a package identified in a previous TYPE statement.

IN A statement identifying the names of input pins attached to only one node (see NODE Statement)

IN_SHR A statement identifying the names of input pins attached to more than one node (see NODE Statement)

OUT A statement identifying the names of output pins attached to only one node (see NODE Statement)

OUT_SHR A statement identifying the names of output pins attached to more than one node (see NODE Statement)
 

IO A statement identifying the names of bidirectional pins attached to only one node (see NODE Statement)

IO_SHR A statement identifying the names of bidirectional pins attached to more than one node (see NODE Statement)

PWR A statement identifying the names of pins supplying power to the package

GND A statement identifying the names of pins providing ground to the package

NODE A statement identifying connections within the package between pins (inputs to outputs)

END A statement identifying the end of a package specification

The statements in the file are divided into units which specify the connectivity of different package types. Each unit begins with a TYPE statement and ends with either another TYPE statement or an END statement. Within a specification unit all the IN, OUT, IO and other pin type statements must precede all the NODE statements.

The IN, OUT, IO and other pin type statements identify all the pins in the package. Each pin name may appear in only one of these statements. The pin names in these statements must be exactly the same as those in the (EDIF file) design to be translated. The types may be different from the pin types in the design.

Each NODE statement identifies a separate set of circuits that interconnect input and output pins. Typically, a NODE represents an independent circuit such as a NAND gate, a Flip Flop or a buffer. It may also represent a resister in a resistor pack.

The pins identified as PWR and GND are assumed to affect all the outputs identified in NODE statements. A pin may not appear in more than one NODE unless it is identified in an IN_SHR, OUT_SHR or IO_SHR statement. Clocks and other pins which affect more than one circuit in the package would fall into this category.

The following is an example of the contents of a Package Library File: