1. LASAR/Guided probe has difficulty handling large, complicated circuits, because of modeling limitations.

2. All modeling must be done at the gate level, which is time consuming and error prone. Although gate-level models are often available for chips, they are often not available, also. Gate level modeling takes a long time. For example, on the board that we are dealing with, it took about 5 manyears to do the modeling for the board.

3. The fault dictionary lookup is often confused by specific faults that were not simulated or by multiple faults.

4. Since Guided Probe requires probing at each pin, it is a time-consuming, labor intensive process, and results in long test times. It is very manual.

5. Diagnostic Effectiveness often falls short.

6. Process requires nodal verification to verify the model, which is also a time-consuming process.

7. The quality of the diagnostics is largely dependent upon the faults that were defined in the fault simulation process. If faults that were not modeled occur, or if multiple faults occur, then effective diagnostics are not achieved.

8. Sometimes it is not practical to implement fault dictionary / guided probe approaches, due to inadequate modeling data to work with, the time required for modeling, or guided probe is deemed to be too slow of a process, given the board size (pin count).

9. Also sometimes, not all internal points can be probed due to conformal coating, tight physical spacing, etc.

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Last modified: July 05, 2000